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d a t a sh eet product speci?cation file under integrated circuits, ic02 january 1987 integrated circuits SAA5250 interface for data acquisition and control (for multi-standard teletext systems)
january 1987 2 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 general description the SAA5250 is a cmos interface for data acquisition and control (cidac) designed for use in conjunction with the video input processor (saa5230) in a multi-standard teletext decoder. the device retrieves data from a user selected channel (channel demultiplexer), as well as providing control signals and consecutive addressing space necessary to drive a 2 k bytes buffer memory. the system operates in accordance with the following transmission standards: french didon antiope specification d2 a4-2 (didon) north american broadcast teletext specification (nabts) u.k. teletext (ceefax) features 7,5 mhz maximum conversion rate three prefixes; didon, nabts and u.k. teletext (ceefax) mode without prefix internal calculation of the validation (val) and colour burst blanking (cbb) signals, if programmed programmable framing code and channel numbers error parity calculation or not (odd parity) hamming processing of the prefix byte full channel or vbi reception slow/fast mode (detection of page flags or not) maximum/default format up to 63 bytes addressing space of 2 k bytes of the static memory multiplexed address/data information is compatible with motorola or intel microcontrollers cidac is motel compatible package outlines SAA5250p: 40-lead dil; plastic (sot129); sot129-1; 1996 december 02. SAA5250t: 40-lead mini-pack; plastic (vso40); sot158-1; 1996 december 02.
january 1987 3 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 k , full pagewidth mgh075 framing code detection serial register clock generation serial/parallel converter hamming corrector sequence controller parallel register validation signal processing format processor 2 k byte fifo memory controller format transcoder format counter memory interface channel comparator program register register page detection interface 17 9-16 18 21 19 db7 to db0 ale cs rd wr 78 1, 39-30 29-22 40 20 11 8 ms we a10 to a0 d7 to d0 v dd v ss 4 2 3 5 dck 6 sd val in/ sync val out cbb SAA5250 8 fig.1 block diagram.
january 1987 4 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.2 pinning diagram. handbook, halfpage SAA5250 mgh074 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v dd a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 rd a10 val out val in/ sync cbb dck sd ms we db7 db6 db5 db4 db3 db2 db1 db0 ale cs wr v ss
january 1987 5 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 pinning function mnemonic pin no. function a10 and a0 to a9 1 and 30 to 39 memory address outputs used by cidac to address a 2 k byte buffer memory val out 2 validation output signal used to control the location of the window for the framing code. val in/sync 3 validation input signal (line signal) used to give or calculate a window for the framing code detection cbb 4 colour burst blanking output signal used by the saa5230 as a data slicer reset pulse dck 5 data clock input, in synchronization with the serial data signal sd 6 serial data input, arriving from the demodulator ms 7 chip enable output signal for buffer memory selection we 8 write command output for the buffer memory db7 to db0 9 to 16 8-bit three state input/output data/address bus used to transfer commands, data and status between the cidac registers and the cpu ale 17 demultiplexing input signal for the cpu data bus ce 18 chip enable input for the SAA5250 wr 19 write command input (when low) v ss 20 ground rd 21 read command input (when low) d0 to d7 22 to 29 8-bit three state input/output data bus used to transfer data between cidac and the buffer memory v dd 40 + 5 v power supply
january 1987 6 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 functional description microcontroller interface the microcontroller interface communicates with the cpu via the handshake signals db7 - db0, ale, cs, rd, wr. the microcontroller interface produces control commands as well as programming the registers to write their contents or read incoming status/data information from the buffer memory. the details of the codes used to address the registers are given in table 2. the cidac is motel compatible (motel compatible means it is compatible with standard mo torola or in tel microcontrollers). it automatically recognizes the microcontroller type (such as the 6801 or 8501) by using the ale signal to latch the state of the rd input. no external logic is required. table 1 recognition signals table 2 cidac register addressing cidac 8049/8051 timing 1 6801/6805 timing 2 ale ale as rd rd ds, e, f 2 wr wr r/ w codes function r w cs db2 db1 db0 100000 write register r0 100001 write register r1 100010 write register r2 100011 write register r3 100100 write register r4 100101 write register r5 100110 write command register r6 (initialization command) 100111 write register r7 010000 read status 010001 read data register 010010 test (not used) 010011 test (not used)
january 1987 7 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 register organization r0 register table 3 r0 register contents all of the bytes (see fig.3) are hamming protected. the hatched bytes are always stored in the memory in order to be processed by the cpu (see section prefix processing). in the mode without prefix all of the bytes which follow the framing code are stored in the memory until the end of the data packet, the format is then determined by the contents of the r3 register. if r03 = 0; no parity control is carried out and the 8-bits of the incoming data bytes are stored in the fifo memory. if r03 = 1; the 8th bit of the bytes following the prefix (data bytes) represents the result of the odd parity control. if r04 = 0; the device operates in the slow mode. the cidac retrieves data from the user selected magazine (see section r1 and r2) and without searching for a start to a page stores the data into the fifo memory. r04 slow/fast mode r03 parity r02 to r00 used prefixes 0 = slow mode 0 = no parity control 000 = didon long 1 = fast mode 1 = odd parity 001 = didon medium 010 = didon short 011 = not used 100 = u.k. teletext 101 = nabts 110 = without pre?x 111 = without pre?x fig.3 five prefixes. handbook, full pagewidth mgh077 ci format a3 a2 a2 format a1 a1 a fc fc fc fc ceefax didon short didon medium didon long ci ps a3 a2 a1 fc nabts magazine and row address group mrag
january 1987 8 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 if r04 = 1; the device operates in the fast mode. prior to writing into the fifo memory, the cidac searches for a start to a page which is variable due to the different prefixes: didon (long, medium and short): using the redundant bytes, soh rs, x rs and soh x (where x is a bit affected by a parity error) nabts, the least significant bit of the ps byte is set to 1 u.k. teletext, row = 0 r1 register table 4 r1 register contents note 1. x = dont care if val in/sync = 1; the line signal immediately produces a validation signal for the framing code detection. if val out = 0; the line signal is used as a starting signal for an internally processed validation signal (see fig.15). the framing code window width is fixed at 13 clock periods and the delay is determined by the contents of the r5 register (r56 to r50). at any moment the user is able to ensure that the framing code window is correctly located. this is accomplished by the val out pin reflecting the internal validation signal. a cbb signal with programmable width (see section r7 register) can also be generated, this is used as a data slicer reset pulse by the saa5230. the line signal is used as the starting point of the internal cbb signal width fixed by the contents of the r7 register. if r16 = 0; then bits r15 and r14 provide the format table number using didon long and short prefixes (see table 6). if r16 = 1; then the format is determined by the contents of the r3 register. the bits r13 to r10 represent the first channel number to be checked in the prefix. in u.k. teletext mode only 3 bits are required, so r13 = x. r17 val in/sync r16 to r14 format table (1) r13 to r10 channel numbers (first digit) 1 = val 000 = list 1 ?rst digit hexadecimal value 0 = sync 001 = list 2 010 = list 3 011 = list 4 1xx = maximum/default value used (r3)
january 1987 9 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 table 5 format table note 1. b8 = msb and b2 = lsb. r2 register table 6 r2 register contents note 1. r27 and r23 = msb and r24 and r20 = lsb the r2 register provides the other two parts of the channel number (depending on the prefix) that require checking. format byte b8, b6, b4 and b2 (1) list 1 list 2 list 3 list 4 0000 0 0 0 0 0001 1 1 1 1 0010 2 2 2 2 0011 3 3 3 3 0100 4 5 6 7 0101 8 9 10 11 0110 12 13 14 15 0111 16 17 18 19 1000 20 21 22 23 1001 24 25 26 27 1010 28 29 30 31 1011 3233 3435 1100 36 37 38 39 1101 40 41 42 43 1110 44 45 46 47 1111 48 49 50 51 r27 to r24 r23 to r20 channel number, third digit channel number, second digit (hexadecimal value, third digit) (hexadecimal value, second digit
january 1987 10 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 r3 register table 7 r3 register contents this 6-bit byte gives: in the didon long and short mode, a maximum format in case of corrupted transmission (multiple errors on the hamming corrector) a possible 63-bit format for all types of prefix r4 register table 8 r4 register contents r5 register table 9 r5 register contents note 1. f = data clock acquisition frequency (dck). using r57 it is possible to start the internal synchronization delay (t dval ) on the positive or negative edge. r6 write command register this is a fictitious register. only the address code (see table 2) is required to reset the cidac. see table 11 for the status of the fifo memory on receipt of this command. r7 register table 10 r7 register contents note 1. f = data clock acquisition frequency. r35 to r30 6-bit format maximum/default value 000000 = 0 000001 = 1 - - - 111111 = 63 r47 to r40 8-bit register used for storing the framing code value which will be compared with the third byte of each data line r57 negative/positive r56 to r50 synchronization delay 0 = negative edge for sync signal 7-bit sync delay, giving a maximum 1 = positive edge for sync signal delay of (2 7 - 1) 10 6 m s/f (hz) r75 to r70 6-bit register used to give a maximum colour burst blanking signal of: (2 6 - 1) 10 6 m s/f (hz)
january 1987 11 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fifo status register ( read r0 register) table 11 fifo register contents once the relevant prefix and the right working modes have been given by the corresponding registers, a write command to the r6 register enables the cidac to accept and process serial data. channel comparator this is a four bit comparator which compares the three user hexadecimal defined values in r1 and r2 to corresponding bytes of the prefix coming from the hamming corrector. if the three bytes match, the internal process of the prefix continues. if they do not match the cidac returns to a wait state until the next broadcast data package is received. fifo memory controller the fifo memory contains all the necessary functions required for the control of the 11-bit address memory (2 k byte). the functions contained in the fifo memory are as follows: write address register (11-bits) read address register (11-bits) memory pointer (11-bits) address multiplexer (11-bits) write data register (8-bits) read data register (8-bits) data multiplexer control logic the fifo memory provides the memory interface with the following: 11-bit address bus (a10 to a0) 8-bit data bus (d7 to d0) two control signals, memory select ( ms) and write enable ( we) db2 to db0 db2 = 1 memory empty db1 = 1, data not present in the read data register db0 = 0 memory not full
january 1987 12 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 operation the cidac uses the same clock signal for data acquisition and internal processing, this allows the cidac to have a write and a read cycle during each character period (see fig.13). the first half of the character period is a write cycle and the second half is a read cycle. consequently, for an 8 mhz bit rate the maximum memory cycle time is 500 ns. when the first data byte is written into the fifo memory, thus transferred into the read register, the fifo memory enters the status shown in table 12. table 12 fifo status when the fifo memory is full two events occur: the write address register points to the next address after the last written address when new data is to be written, the memory select signal output ceases memory interface the memory interface contains all the buffers for the memory signals mentioned in the section fifo memory controller. page detection this part of the cidac contains a parallel register with logic which detects (only in fast mode) a start of a page or data group (see section r0 register). hamming correction (see tables 13 and 14) the hamming correction provides (see section prefix processing): hexadecimal value of the hamming code accept/reject code signal parity information db2 to db0 db2 = 1 memory empty db1 = 0 data available db0 = 0 memory not full
january 1987 13 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 table 13 hamming correction (coding) note 1. b7 = b8 ? b6 ? b4 b5 = b6 ? b4 ? b2 b3 = b4 ? b2 ? b8 b1 = b2 ? b8 ? b6 ? = exclusive or gate function b8, b6, b4 and b2 = data bits b7, b5, b3 and b1 = redundancy bits hexadecimal notation b8 b7 b6 b5 b4 b3 b2 b1 0 00010101 1 00000010 2 01001001 3 01011110 4 01100100 5 01110011 6 00111000 7 00101111 8 11010000 9 11000111 a 10001100 b 10011011 c 10100001 d 10110110 e 11111101 f 11101010
january 1987 14 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 table 14 hamming correction (decoding) note 1. a = b8 ? b6 ? b2 ? b1 b = b8 ? b4 ? b3 ? b2 c = b6 ? b5 ? b4 ? b2 d = b8 ? b7 ? b6 ? b5 ? b4 ? b3 ? b2 ? b1 ? = exclusive or gate function format processing the format processing consist of two parts: part 1 a format transcoder produces a 6-bit code (up to 63) and uses the following as inputs: didon long and short prefixes; hamming corrected code (4-bits) accept/reject code condition table number (see section r1 register, bits r15 and r14) other prefixes (r16 = 1) 6-bit maximum/default format (see section r3 register) part 2 a format counter operating at the character clock frequency which receives the 6-bit code from the format transcoder and is used to check the data packet length following the prefix. serial/parallel converter the serial/parallel converter consists of three parts: an 8-bit shift register which receives the sd input and operates at the bit frequency (dck). an 8-bit parallel register used for storage. a framing code detection circuit. this logic circuit compares the 8-bits of the r4 register with that of the serial register. if seven bits out of eight match (in coincidence with a validation window), it produces a start signal for a new teletext data line to the sequence controller. abcd interpretation information 1111no error accepted 0010 error on b8 corrected 1110 error on b7 accepted 0100 error on b6 corrected 1100 error on b5 accepted 1000 error on b4 corrected 1010 error on b3 accepted 0000 error on b2 corrected 0110 error on b1 accepted a.b.c = 0 1 multiple errors rejected
january 1987 15 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 clock generation the clock generator does the following: acts as a buffer for the dck clock generates the character clock as soon as a framing code has been detected, a divide by 8 counter is initialized and the character clock is started. the clock drives the following: sequence controller parallel registers format counter processing of val and cbb signals the circuit has one input (val in/sync) and two outputs (val out and cbb). the circuit consists of: 7-bit counter operating at dck frequency which produces the framing code validation pulse delay 7-bit comparator which compares the contents of the r5 register (bits r56 to r50) to the bit counter a 6-bit counter operating at dck frequency which produces the cbb pulse width 6-bit comparator which compares the contents of the r7 register (bits r75 to r70) to the bit counter control logic required to provide the start condition for the val signal and the cbb pulse width (on the negative or positive edge of the sync signal) the cbb signal useful occurs when the associated video processor: has no sandcastle pulse to send back to the demodulator carries out the synchronization of the time base clock. in this event the cbb acts as a data slicer reset pulse the val out is a control signal which reflects the internal framing code window. pre?x processing (see table 21) figs 4 to 9 show the acquisition flow charts for each prefix type coded in the r0 register (bits r02 to r00). as soon as an initialization command is received by the cidac, a write command to the r6 register (only the address is significant), is ready to receive data from a dedicated channel number and store the data in the fifo memory (explained in the following paragraphs, each paragraph being dedicated to an individual type of prefix). didon long (see fig.4) in this mode, the continuity index, format and data bytes are written into the fifo memory. (in fast mode, information can be written into the fifo memory only after a page detection.)
january 1987 16 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 table 15 continuity index processing result table 16 format processing result note 1. a/r = 0, if rejected 2. a/r = 1, if accepted 3. x = dont care didon mediun (see fig.5) only data bytes are written into the fifo memory. (in fast mode, information can be written into the fifo memory only after a page detection.) didon short (see fig.6) in this mode, format and data bytes are written into the fifo memory. (in fast mode, information can be written into the fififo memory only after a page detection.) table 17 format processing result nabts (see fig.7) in this mode, the continuity index, packet structure and data bytes are written into the fifo memory. (in fast mode, information can be written into the fifo memory only after a page detection.) table 18 continuity index processing result table 19 packet structure processing result u.k. teletext (see fig.8) in this mode, the magazine and row address group (two bytes) and data bytes are written into the fifo memory. (in fast mode, information can be written into the fifo memory only after a flag detection.) d7 d6 d5 d4 d3 d2 d1 d0 a/r x x x ci3 ci2 ci1 ci0 d7 d6 d5 d4 d3 d2 d1 d0 a/rx f5f4f3f2f1f0 d7 d6 d5 d4 d3 d2 d1 d0 a/rx f5f4f3f2f1f0 d7 d6 d5 d4 d3 d2 d1 d0 a/r x x x ci3 ci2 ci1 ci0 d7 d6 d5 d4 d3 d2 d1 d0 a/r x x x ps3 ps2 ps1 ps0
january 1987 17 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 table 20 magazine and row address group processing results without pre?x all the data following the framing code are stored in the fifo memory. table 21 pre?x processing note 1. after page/flag detection 2. a1, a2, a3 are channel numbers ci = continuity index f = format ps = packet structure d = data mrag = magazine and row address group d7 d6 d5 d4 d3 d2 d1 d0 a/r x x rw4 rw3 rw2 rw1 rw0 prefixes construction of prefixes bytes stored in fifo memory during slow mode bytes stored in fifo memory during fast mode didon long a1, a2, a3, ci, f and d ci, f and d ci (1) , f (1) and d (1) didon medium a1, a2 and d d d (1) didon short a1, f and d f and d f (1) and d (1) nabts a1, a2, a3 ci, ps and d ci, ps and d ci (1) , ps (1) and d (1) u.k. teletext mrag and d mrag and d mrag (1) and d (1) without pre?x all bytes of the data packet following the framing code are written into the fifo memory
january 1987 18 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.4 didon (long) acquisition flow chart.
january 1987 19 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.5 didon (medium) acquisition flow chart. handbook, full pagewidth initialize cidac load format counter with explicit value decrement format counter. write data bytes into fifo framing code detect a2 o.k. format counter = 0 decrement format counter set page in progress flag 1 0 a1 o.k. 1 0 1 0 1 page in progress slow/fast mode 0 0 1 1 0 start of page detect slow fast mgh084
january 1987 20 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.6 didon (short) acquisition flow chart. handbook, full pagewidth initialize cidac load format counter with incoming value decrement format counter. write data bytes into fifo framing code detect format counter = 0 decrement format counter set page in progress flag write format into fifo 0 1 1 0 a o.k. 1 0 page in progress slow/fast mode 0 1 0 0 1 format counter = 0 1 start of page detect slow fast mgh083
january 1987 21 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.7 nabts acquisition flow chart. handbook, full pagewidth mgh082 set data group in progress flag initialize cidac load format counter with implicit format decrement format counter. write data bytes into fifo framing code detect format counter = 0 save ci bytes write ci byte into fifo write ps byte into fifo 0 1 1 0 a1 o.k. 1 a2 o.k. 1 0 0 0 data group in progress slow/fast mode 0 1 1 synchronizing packet 0 a3 o.k. 1 slow fast
january 1987 22 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.8 u.k. teletext acquisition flow chart. handbook, full pagewidth mgh081 set page in progress flag initialize cidac load format counter with implicit format decrement format counter. write data bytes into fifo framing code detect format counter = 0 1 0 mag o.k. 1 0 page in progress slow/fast mode 0 1 row 0 0 slow write row number into fifo
january 1987 23 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.9 without prefix acquisition chart. handbook, halfpage mgh080 initialize cidac load format counter with explicit format decrement format counter. write data bytes into fifo framing code detect format counter = 0 0 1 1 0 fig.10 sd and dck input circuitry. handbook, full pagewidth mgh076 d d cbi 5 6 d = clamping diodes cbi = clamping pulse, the pulse width is given by the r7 register clock input to data acquisition circuit data input to data acquisition circuit dck sd
january 1987 24 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 ratings limiting values in accordance with the absolute maximum system (iec 134) d.c. characteristics (except sd and dck) v dd = 5 v 10%; v ss = 0 v; t amb = 0 to 70 c, unless otherwise speci?ed parameter conditions symbol min. max. unit supply voltage range v dd - 0,3 6,5 v input voltage range v i - 0,3 v dd + 0,3 v total power dissipation p tot - 400 mw operating ambient temperature range t amb 070 c storage temperature range t stg - 20 + 125 c parameter conditions symbol min. typ. max. unit supply voltage range v dd 4,5 5,0 5,5 v input voltage high v ih 2 - v dd v input voltage low v il -- 0,8 v input leakage current i i -- 1,0 m a output voltage high i load = 1 ma v oh v dd - 0,4 -- v output voltage low i load = 4 ma, at pins 9 to 16 and 22 to 29 v ol -- 0,4 v i load = 1 ma all other outputs v ol -- 0,4 v power dissipation p - 5 - mw input capacitance c i -- 7,5 pf
january 1987 25 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 sd and dck d.c. characteristics (see fig.10) v dd = 5 v; v ss = 0 v; t amb = 0 to 70 c, unless otherwise speci?ed parameter conditions symbol min. typ. max. unit dck input voltage range (peak-to-peak value) v i(p-p) 2,0 -- v input current v i = 0 to v dd i i 5 - 200 m a input capacitance c i -- 30 pf external coupling capacitor c text 10 -- nf sd d.c. input voltage range high note 1 v ih 2,0 -- v d.c. input voltage range low note 2 v il -- 0,8 v a.c. input voltage (peak-to-peak value) v i(p-p) 2,0 -- v input leakage current v i = 0 to v dd i i -- 10 m a input capacitance c i -- 30 pf external coupling capacitor c ext 10 -- nf
january 1987 26 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 a.c. characteristics v dd = 5 v 10%; reference levels for all inputs and outputs, v ih = 2 v; v il = 0,8 v; v oh = 2,4 v; v ol = 0,4 v; c l = 50 pf on db7 to db0; t amb = 0 to 70 = c, unless otherwise speci?ed parameter conditions symbol min. typ. max. unit microcontroller interface figs 11 and 12 cycle time t cy 400 -- ns address pulse width t lhll 50 -- ns rd high or wr to ale high fig.11 t ahrd 0 -- ns ds low to as high fig.12 t ahrd 0 -- ns ale low to rd low or wr low fig.11 t alrd 30 -- ns as low to ds high fig.12 t alrd 30 -- ns write pulse width t wl 120 -- ns address and chip select set-up time t asl 10 -- ns address and chip select hold time t ahl 20 -- ns read to data out period t rd -- 130 ns data hold after rd t dr 10 - 100 ns r/ w to ds set-up time fig.12 t rws 40 -- ns r/ w to ds hold time fig.12 t rwh 10 -- ns data set-up time write cycle t dw 50 -- ns data hold time write cycle t wd 10 -- ns read pulse width note 3 t rl 150 or dck + 50 -- ns memory interface fig.13 we low to dck falling edge t wel 10 - 80 ns we high to dck falling edge t weh 10 - 80 ns ms low to dck rising edge t msl 10 - 80 ns ms high to dck rising edge t msh 10 - 85 ns address output from dck rising edge t av 10 - 120 ns data output from we falling edge t dwl 0 - 10 ns data hold from we rising edge t dwh 0 -- ns address set-up time to data note 4 t ad -- 3 dck - 110 ns we pulse width note 5 t wew 3 dck -- ns ms pulse width note 6 t msw 2 dck -- ns
january 1987 27 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 notes to the characteristics 1. unless r7 = 00 the value given is unacceptable. 2. when cbi signal is maintained at 0 v (r7 = 00) and if sd input signal is correctly referenced to ground, no coupling capacitor is required. 3. dck + 50 is the dck period plus 50 ns. 4. 3 dck - 110 is 3 dck period - 110 ns. 5. 3 dck is 3 dck period. 6. 2 dck is 2 dck period. 7. x = irrelevant. demodulator interface (see sd and dck d.c. characteristics) fig.14 dck low conversion rate < 7,5 mhz t dckl 55 -- ns dck high conversion rate < 7,5 mhz t dckh 55 -- ns serial data set-up time t ssd 0 -- ns serial data hold time t hsd 30 -- ns validation signal set-up time t svali 50 -- ns validation signal hold time t hvali 50 -- ns other i/o signals fig.15 user de?nable width as a multiple of dck period t wcbb 0 - 63 dck validation signal width note 7 t wval x 12 x dck user de?nable delay as a multiple of dck period t dval 0 - 127 dck parameter conditions symbol min. typ. max. unit
january 1987 28 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.11 timing diagram for microcontroller interface (intel). handbook, full pagewidth bus cs wr rd ale read cycle t ahrd t lhll t asl t rd t alrd t rl t cy t ahl t dr address d out bus cs rd wr ale write cycle t ahrd t ahrd t lhll t asl t dw t alrd t wl t cy t ahl t wd address d in mgh087
january 1987 29 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.12 timing diagram for microcontroller interface (motorola). handbook, full pagewidth mgh085 d in d out t dr t wd t dw t rd t ahl t asl t asl t ahl t rws t lhll t ahrd t alrd t ahrd t rwh t cy bus bus read cycle write cycle cs r/w (pin wr) as (pin ale) ds (pin rd) (1) (1) (1) ale, cs, rd, wr and db7 to db0
january 1987 30 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 handbook, full pagewidth mgh086 t msw t ad t wew t wel t weh t msl t msl t dwl t av t msh t av t dwh data out data in read address write address data out write address d7 to d0 a10 to a0 ms we dck character period fig.13 timing diagram for memory interface.
january 1987 31 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 fig.14 timing diagram for demodulator interface. handbook, full pagewidth mgh079 t dckl t ssd t dckh t hsd t hvali t svali dck sd val in/ sync fig.15 timing diagram for all other i/o signals. handbook, full pagewidth mgh078 t wcbb t dval t wval clock synchronization bits framing code prefix and data bytes cbb val out sd val in / sync dck val, cbb
january 1987 32 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot129-1 92-11-17 95-01-14 a min. a max. b z max. w m e e 1 1.70 1.14 0.53 0.38 0.36 0.23 52.50 51.50 14.1 13.7 3.60 3.05 0.254 2.54 15.24 15.80 15.24 17.42 15.90 2.25 4.7 0.51 4.0 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.12 0.01 0.10 0.60 0.62 0.60 0.69 0.63 0.089 0.19 0.020 0.16 051g08 mo-015aj m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 40 1 21 20 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
january 1987 33 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 unit a 1 a 2 a 3 b p cd (1) e (2) z (1) eh e ll p qy w v q references outline version european projection issue date iec jedec eiaj mm inches 0.3 0.1 2.45 2.25 0.25 0.42 0.30 0.22 0.14 15.6 15.2 7.6 7.5 0.762 2.25 12.3 11.8 1.15 1.05 0.6 0.3 7 0 o o 0.1 0.1 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 1.7 1.5 sot158-1 92-11-17 95-01-24 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a y 40 20 21 1 pin 1 index 0.012 0.004 0.096 0.089 0.017 0.012 0.0087 0.0055 0.61 0.60 0.30 0.29 0.03 0.089 0.48 0.46 0.045 0.041 0.024 0.012 0.004 0.2 0.008 0.004 0.067 0.059 0.010 0 5 10 mm scale vso40: plastic very small outline package; 40 leads sot158-1 a max. 2.70 0.11
january 1987 34 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so and vso r eflow soldering reflow soldering techniques are suitable for all so and vso packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. w ave soldering wave soldering techniques can be used for all so and vso packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
january 1987 35 philips semiconductors product speci?cation interface for data acquisition and control (for multi-standard teletext systems) SAA5250 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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